Mealy model in Verilog for Sequential Circuits
Posted: Sat Nov 14, 2009 9:54 pm
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module Mealy_mdl (x,y,CLK,RST);
input x,CLK,RST;
output y;
reg y;
reg [1:0] Prstate, Nxtstate;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @ (posedge CLK or negedge RST)
if (~RST) Prstate = S0; //Initialize to state S0
else Prstate = Nxtstate; //Clock operations
always @ (Prstate or x) //Determine next state
case (Prstate)
S0: if (x) Nxtstate = S1;
S1: if (x) Nxtstate = S3;
else Nxtstate = S0;
S2: if (~x)Nxtstate = S0;
S3: if (x) Nxtstate = S2;
else Nxtstate = S0;
endcase
always @ (Prstate or x) //Evaluate output
case (Prstate)
S0: y = 0;
S1: if (x) y = 1'b0; else y = 1'b1;
S2: if (x) y = 1'b0; else y = 1'b1;
S3: if (x) y = 1'b0; else y = 1'b1;
endcase
endmodule