Behavioral Modeling of Free Running Clock in Verilog
Posted: Sat Nov 14, 2009 9:09 pm
//An example of a free-running clock
initial
begin
clock = 1’b0;
repeat (30)
#10 clock = ~clock;
end
initial
begin
clock = 1’b0;
#300 $finish;
end
always
#10 clock = ~clock
initial
begin
clock = 1’b0;
repeat (30)
#10 clock = ~clock;
end
initial
begin
clock = 1’b0;
#300 $finish;
end
always
#10 clock = ~clock