I just reviewed this method on PROM synthesizing, but this seems little bit odd.
src : http://www.cs.ucr.edu/~dalton/i8051/i80 ... 51_rom.vhd
Code: Select all
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use WORK.I8051_LIB.all;
entity I8051_ROM is
port(rst : in STD_LOGIC;
clk : in STD_LOGIC;
addr : in UNSIGNED (11 downto 0);
data : out UNSIGNED (7 downto 0);
rd : in STD_LOGIC);
end I8051_ROM;
architecture BHV of I8051_ROM is
type ROM_TYPE is array (0 to 541) of UNSIGNED (7 downto 0);
constant PROGRAM : ROM_TYPE := (
"00000010", -- LJMP
"00000000",
"11001010",
"10001011", -- MOV_9
"00010010",
"10001010", -- MOV_9
"00010011",
...
begin
process(rst, clk)
begin
if( rst = '1' ) then
data <= CD_8;
elsif( clk'event and clk = '1' ) then
if( rd = '1' ) then
data <= PROGRAM(conv_integer(addr));
else
data <= CD_8;
end if;
end if;
end process;
end BHV;
I think that is good for only simulating purposes. I don't think that would work in real chip ,
Any idea to use Xilinix platform PROM directly ?