16FXXX MidRange Instruction Set Explained

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SemiconductorCat
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16FXXX MidRange Instruction Set Explained

Post by SemiconductorCat » Thu May 17, 2012 12:10 pm

16FXXX Mid Range MicroChip Instruction set Explained.
=====================================================

There is nothing magic of a instruction in assembly language. It's
name precisely explains what it really does. Not only microchip but
on other microprocessors and microcontrollers. There is a pattern, when
you keep that pattern into your head,you don't need to keep the
instruction set in your head either. [In that case Microchip have done
a excellent job, to make the instruction set very easy].


A instruction in assembly language contains two parts ,
1. Menomonic part. [ex- MOVLF , IXORF , MOVLW ....]
2. Parameter(s) part. [ f,d ,0x89 etc ....]


In Microchip PIC16FXXX(mid range), The first 2-4 letters in the instruction
contains it's operation , example.

[bellow , most of these instructions are contain 3 letter's which related to it's operation].

ADD
AND
CLR -clear
COM - compare
DROBOT.LK - decrement
IOR - inclusive or
XOR - exclusive or
NOP - no operation.


[bellow ,some of these instructions are contain 2 letter's which related to it's operation].
BC - Bit clear
BS - bit set
BT - bit test
RL - rotate left
RR - rotate right

[bellow instructions contain 4 letter's which are related to it's operation].
CALL
GOTO
SWAP
.. etc.



And the letters normally contain letters , LW , WF or SC , SC
Where ,
L - literial
F - general purpose register or memory.
W - W register [this is not a general purpose register ]
SC - Skip if bit was clear.if bit =0.
SS - Skip if bit was set. if bit =1.

LW - literial with a working register.
WF - Working register W with memory register/ ram memory.

[*NOTE THAT THERE ARE NO 'LF' just because of the limitations of the
midrange MCU's. And also to keep instruction set simple.]

Please note that only the register W is not memory mapped in this
midrange (16FXXX) architecture. Even the STATUS register was mapped to
a memory location. Typically it exists on all banks , because it was used
to switch between banks.




So let's jump into some examples,

Code: Select all

ADDWF STATUS , 1
Operation is 'ADD' and W , F ( Here STATUS register is located in memory ) registers and
store it according to the value of d, In here because d=1, it will be stored back to
the STATUS register.

Please note that 'd'(the second parameter '1') is just a bit here. Where it contains the
direction of the data flow.If d=0, then it will be stored back to the register W and ,
register STATUS will remain as it was before the instruction.

Code: Select all

ANDLW 0x0F
W register's upper nibble will be masked out. For a example if w=b11011010 before the
instruction executed, then after instruction executed it will be w=b00001010 , where
it's all upper nibble will be masked out.

We use AND operation for masking things like that.Example your reading only first
4 bits of a A/D module or a timmer.

Code: Select all

      BTFSS STATUS ,Z
      RETLW 1
zero: 
      RETLW 0
For a example, suppose you have added two numbers , if the result is zero, then you
have to return 1. Otherwise you have to return 0. Could you Understand.

There RETLW , which means return literal on W register. So that pattern applies
everywhere.So from now , I think you have cleared lots of instructions up to this
extend. Rest of the half contains the same pattern, it's up to you.



ADMIN: Could I have more permanent edit permissions on this POST.

-- Hope you Enjoying Reading The Assembly Code--
-- Thanks For Reading--
-- Sandun --
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Re: 16FXXX MidRange Instruction Set Explained

Post by Nandika » Mon May 21, 2012 5:55 am

Nice Tutorial....

Easy to remember and understand according to this command explanation.
I will try to apply this to all commands. :D

Thank.
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