RAM ARCHITECTURE

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Face
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RAM ARCHITECTURE

Post by Face » Fri Apr 09, 2010 7:25 pm

Friend...
I learned a little about RAM/Main memory in my class.

Image

It use electricity to store data.(It is in my Note book :) ) It store Binary numbers inside it.
But friend I don't know how they store binary numbers inside it..???
Can you explain about it.I want to learn....

1.The architecture of the main memory.(hardware things.ex-about transistors.caps it contain..& how they work.)
2.How it store binary numbers using electricity.
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Re: RAM ARCHITECTURE

Post by Neo » Sun Apr 11, 2010 1:55 am

First memory is divided in to two major parts.
  1. Volatile memory
    Also known as volatile storage, is computer memory that requires power to maintain the stored information.
  2. non-Volatile memory
    Memory which does not require a maintained power supply to keep information.
Volatile memory
Volatile memory is divided in to two major types.
  1. Dynamic Random Access Memory (DRAM)

    Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory.

    The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density. Unlike flash memory, it is volatile memory since it loses its data when the power supply is removed. The transistors and capacitors used are extremely small—millions can fit on a single memory chip.

    Operation
    DRAM is usually arranged in a square array of one capacitor and transistor per cell. The illustrations below show a simple example with only 4 by 4 cells (modern DRAM can be thousands of cells in length/width).

    The long lines connecting each row are known as word lines. Each column is actually composed of two bit lines, each one connected to every other storage cell in the column. (The illustration to the right does not include this important detail.) They are generally known as the + and ? bit lines. A sense amplifier is essentially a pair of cross-connected inverters between the bit lines. That is, the first inverter is connected from the + bit line to the ? bit line, and the second is connected from the ? bit line to the + bit line. This is an example of positive feedback, and the arrangement is only stable with one bit line high and one bit line low.
    read.png
    read.png (48.85 KiB) Viewed 16800 times
    To read a bit from a column, the following operations take place:
    1. The sense amplifier is switched off and the bit lines are precharged to exactly matching voltages that are intermediate between high and low logic levels. The bit lines are constructed symmetrically to keep them balanced as precisely as possible.
    2. The precharge circuit is switched off. Because the bit lines are very long, their capacitance will hold the precharge voltage for a brief time. This is an example of dynamic logic.
    3. The selected row's word line is driven high. This connects one storage capacitor to one of the two bit lines. Charge is shared between the selected storage cell and the appropriate bit line, slightly altering the voltage on the line. Although every effort is made to keep the capacitance of the storage cells high and the capacitance of the bit lines low, capacitance is proportional to physical size, and the length of the bit lines means that the net effect is a very small perturbation of one bit line's voltage.
    4. The sense amplifier is switched on. The positive feedback takes over and amplifies the small voltage difference until one bit line is fully low and the other is fully high. At this point, the row is "open" and a column can be selected.
    5. Read data from the DRAM is taken from the sense amplifiers, selected by the column address. Many reads can be performed while the row is open in this way.
    6. While reads proceed, current is flowing back up the bit lines from the sense amplifiers to the storage cells. This restores (refreshes) the charge in the storage cell. Due to the length of the bit lines, this takes significant time beyond the end of sense amplification, and overlaps with one or more column reads.
    7. When done with the current row, the word line is switched off to disconnect the storage capacitors (the row is "closed"), the sense amplifier is switched off, and the bit lines are precharged again.
    write.png
    write.png (58.29 KiB) Viewed 16800 times
    To write to memory, the row is opened and a given column's sense amplifier is temporarily forced to the desired state, so it drives the bit line, which charges the capacitor to the desired value. Due to the positive feedback, the amplifier will then hold it stable even after the forcing is removed. During a write to a particular cell, the entire row is read out, one value changed, and then the entire row is written back in, as illustrated in the figure to the right.

    Ex: DDR, SDRAM
  2. Static Random Access Memory (SRAM)
    Static Random Access Memory (SRAM) is a type of semiconductor memory where the word static indicates that, unlike dynamic RAM (DRAM), it does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit. SRAM exhibits data remanence, but is still volatile in the conventional sense that data is eventually lost when the memory is not powered.
    static.png
    static.png (6.73 KiB) Viewed 16800 times
    Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit. In addition to such 6T SRAM, other kinds of SRAM chips use 8T, 10T, or more transistors per bit. This is sometimes used to implement more than one (read and/or write) port, which may be useful in certain types of video memory and register files implemented with multi ported SRAM circuitry.

    Generally, the fewer transistors needed per cell, the smaller each cell can be. Since the cost of processing a silicon wafer is relatively fixed, using smaller cells and so packing more bits on one wafer reduces the cost per bit of memory.

    Memory cells that use fewer than 6 transistors are possible — but such 3T or 1T cells are DRAM, not SRAM (even the so-called 1T-SRAM).

    Access to the cell is enabled by the word line (WL in figure) which controls the two access transistors M5 and M6 which, in turn, control whether the cell should be connected to the bit lines: BL and BL. They are used to transfer data for both read and write operations. Although it is not strictly necessary to have two bit lines, both the signal and its inverse are typically provided in order to improve noise margins.

    During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell. This improves SRAM bandwidth compared to DRAMs—in a DRAM, the bit line is connected to storage capacitors and charge sharing causes the bitline to swing upwards or downwards. The symmetric structure of SRAMs also allows for differential signalling, which makes small voltage swings more easily detectable. Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time. By comparison, commodity DRAMs have the address multiplexed in two halves, i.e. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down.

    The size of an SRAM with m address lines and n data lines is 2m words, or 2m × n bits.

    Operation
    An SRAM cell has three different states it can be in: standby where the circuit is idle, reading when the data has been requested and writing when updating the contents. The SRAM to operate in read mode and write mode should have "readeability" and "write stability" respectively. The three different states work as follows:
    • Standby
      If the word line is not asserted, the access transistors M5 and M6 disconnect the cell from the bit lines. The two cross coupled inverters formed by M1 – M4 will continue to reinforce each other as long as they are connected to the supply.
    • Reading
      Assume that the content of the memory is a 1, stored at Q. The read cycle is started by precharging both the bit lines to a logical 1, then asserting the word line WL, enabling both the access transistors. The second step occurs when the values stored in Q and Q are transferred to the bit lines by leaving BL at its precharged value and discharging BL through M1 and M5 to a logical 0. On the BL side, the transistors M4 and M6 pull the bit line toward VDD, a logical 1. If the content of the memory were a 0, the opposite would happen and BL would be pulled toward 1 and BL toward 0.
    • Writing
      The start of a write cycle begins by applying the value to be written to the bit lines. If we wish to write a 0, we would apply a 0 to the bit lines, i.e. setting BL to 1 and BL to 0. This is similar to applying a reset pulse to a SR-latch, which causes the flip flop to change state. A 1 is written by inverting the values of the bit lines. WL is then asserted and the value that is to be stored is latched in. Note that the reason this works is that the bit line input-drivers are designed to be much stronger than the relatively weak transistors in the cell itself, so that they can easily override the previous state of the cross-coupled inverters. Careful sizing of the transistors in an SRAM cell is needed to ensure proper operation.
    Bus behaviour
    A RAM memory with an access time of 70 ns will output valid data within 70 ns from the time that the address lines are valid. But the data will remain for a hold time as well (5-10 ns). Rise and fall times also influence valid timeslots with approximately ~5 ns. By reading the lower part of an address range bits in sequence (page cycle) one can read with significantly shorter access time (30 ns).
Non-Volatile memory
Non-volatile memory, nonvolatile memory, NVM or non-volatile storage, is computer memory that can retain the stored information even when not powered. Examples of non-volatile memory include read-only memory, flash memory, most types of magnetic computer storage devices (e.g. hard disks, floppy disks, and magnetic tape), optical discs, and early computer storage methods such as paper tape and punch cards.

Non-volatile memory is typically used for the task of secondary storage, or long-term persistent storage. The most widely used form of primary storage today is a volatile form of random access memory (RAM), meaning that when the computer is shut down, anything contained in RAM is lost. Unfortunately, most forms of non-volatile memory have limitations that make them unsuitable for use as primary storage.

Ex: ROM (PROM, EPROM, EEPROM), Flash memory

EEPROM and FLASH are moslt used today so I would like to add a small description about them.
  • EEPROM
    EEPROM (electrically erasable programmable read-only memory) is user-modifiable read-only memory (ROM) that can be erased and reprogrammed (written to) repeatedly through the application of higher than normal electrical voltage. Unlike EPROM chips, EEPROMs do not need to be removed from the computer to be modified. However, an EEPROM chip has to be erased and reprogrammed in its entirety, not selectively. It also has a limited life - that is, the number of times it can be reprogrammed is limited to tens or hundreds of thousands of times. In an EEPROM that is frequently reprogrammed while the computer is in use, the life of the EEPROM can be an important design consideration.
  • FLASH
    Flash memory is a non-volatile computer storage that can be electrically erased and reprogrammed. It is a technology that is primarily used in memory cards and USB flash drives for general storage and transfer of data between computers and other digital products. It is a specific type of EEPROM (Electrically Erasable Programmable Read-Only Memory) that is erased and programmed in large blocks; in early flash the entire chip had to be erased at once. Flash memory costs far less than byte-programmable EEPROM and therefore has become the dominant technology wherever a significant amount of non-volatile, solid state storage is needed. Example applications include PDAs (personal digital assistants), laptop computers, digital audio players, digital cameras and mobile phones. It has also gained popularity in console video game hardware, where it is often used instead of EEPROMs or battery-powered static RAM (SRAM) for game save data.

    Since flash memory is non-volatile, no power is needed to maintain the information stored in the chip. In addition, flash memory offers fast read access times (although not as fast as volatile DRAM memory used for main memory in PCs) and better kinetic shock resistance than hard disks. These characteristics explain the popularity of flash memory in portable devices. Another feature of flash memory is that when packaged in a "memory card," it is extremely durable, being able to withstand intense pressure, extremes of temperature, and even immersion in water. A trawlerman attempted to trace the owner of a digital camera after it was hauled from the Atlantic seabed in his nets with the photos still intact.

    Although technically a type of EEPROM, the term "EEPROM" is generally used to refer specifically to non-flash EEPROM which is erasable in small blocks, typically bytes. Because erase cycles are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over old-style EEPROM when writing large amounts of data.

    There are two types of Flash memory technologies named NOR and NAND flash.
    The main differences are as follows.
    • The connections of the individual memory cells are different
    • The interface provided for reading and writing the memory is different (NOR allows random-access for reading, NAND allows only page access)
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Magneto
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Re: RAM ARCHITECTURE

Post by Magneto » Sun Apr 11, 2010 10:38 am

Dear Friend ,

Very Basic unit of the RAM is called "D Type Flip Flop". D Type Flip flop is an basic digital electronic component ,
which is consisting of several transistors. In a D type flip flop , you can store one bit. That is
1 or 0. In other world you can store 5V or 0 V. So if you want to store one byte ( i.e. 8 bits) , you want 8 D type flip flops. Like wise if you want to store 1 KB , you must have 1024 * 8 D Flips and also to have a 1 MB memory , you
must have 1024*1024 *8 D Flip Flops.
D Symbot.JPG
D Symbot.JPG (2.62 KiB) Viewed 16764 times
Fig : Symbolic Diagram of D Type Flip Flop


Let we see the architecture of D Type Flip Flop


Symbolic Diagram of a D Type Flip Flop with Logic Gates
flip_flop_gate.JPG
flip_flop_gate.JPG (19.17 KiB) Viewed 16764 times
So from the above figure , you can see D Type Flip Flop is a collection of NAND and NOT gates. Let we now
see the internal circuit of NAND and NOT gates



Transistor arrangement of NAND gate
Nand_sym.JPG
Nand_sym.JPG (4.85 KiB) Viewed 16764 times
Nand.JPG
Nand.JPG (6.91 KiB) Viewed 16764 times

Transistor arrangement of NOT gate
NOT_sym.JPG
NOT_sym.JPG (3.95 KiB) Viewed 16764 times
Not_tra.JPG
Not_tra.JPG (8.01 KiB) Viewed 16764 times
So you can now clearly see , the basic memory unit , which is D Type Flip Flop is a collection of transistors and resistors.
In the picture you attached in your photo , you can see several IC's on top of the memory card. Those IC's have made out
of millions of D type of Flips Flips , which have constructed in a single IC. That mean in otherworld millions of transistors and resistors.



Let now see how this D Type Flip Flop store Binary information ( i.e. 1 and 0 )
truth_table.JPG
truth_table.JPG (2.02 KiB) Viewed 16764 times
If you see the Symbolic Diagram of a D Type Flip Flop , which I attached , you can see two ports called D and Q.
If you apply +5V in D Port (Logic 1) , you can have the +5V (Logic 1) in Q port , until you turn off the supply voltage to the Flip Flop Circuit. If you apply 0V in D Port (Logic 0) , you can have the 0V (Logic 0) in Q port , until you turn off the supply voltage to the Flip Flop Circuit as this is because of a property of transistor. So in this way you can store the
values of Logic 1 and 0.

You can also make a simple RAM on your own , which can store one or few bytes of information , with electronic components available in Sri Lanka.

Let say if you want to design a circuit , which want to store one byte of information. as a example let say you want to
store the number of 186.

In binary form , it is 10111010. So you have 8 bits and you want a circuit which have 8 D type flip flops. Nowadays ,
for making Flip Flops , you do not want to worry about making circuits with transistors and resistors, Because
there are IC's available in the market , which have inbuilt 1 or more Flip Flops. Then you just want to give power and
signals to those IC's ,and you can directly have the output from the output pins of the IC's.

74ALVC574 is a Digital IC ,available in Sri Lanka Market , which have 8 D Type Flips.
ic.JPG
ic.JPG (8.8 KiB) Viewed 16764 times
Fig : 74ALVC574

So you can easily store one byte of information with this IC. so you can store numbres upto 255 (in binary 11111111)
Just connect 8 swithches to D0 to D7 pins , which can give 0V and 5V , for each pin. Then on and off the swithes
, according to the number you want to store. then number will store in the IC and you take it any time from Q0 to Q7
pins.
So if you want to store the number 186 ( 10111010 in binary) , OFF D0 switch , ON D1 switch , OFF D2 switch , ON D3 switch , ON D4 switch , ON D5 switch , OFF D6 switch , ON D7 switch . Then number 186 will store in the IC and
you can have it from Q0 to Q7 pins.

Now you have made a simple RAM on your own. :D :D :D :D :D :D :D :D :D

So always try to familiar with basic principals of electronics , both digital and analog. Then you can design even complex circuits like Cellular Phones also :D :D

Ragards,
Magneto
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Re: RAM ARCHITECTURE

Post by Face » Sun May 09, 2010 7:31 pm

thank you every one...today I read it all again.Got little idea.But you know that I am not clever in it to understand it completely.But from these posts I got some to my mind.Still beginner na ;)

I know little about LOGIC GATES..& transistors process.From that knowledge I tried to understand this.Thank you all..
I have only Theory knowledge NO any practical knowledge..EXPERTCORE is the first place I learn electronics lessons.. :D

Thank you for all.
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