Verilog Code for 4 bit Binary Counter with Parallel Load

Field-Programmable Gate Arrays
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Magneto
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Verilog Code for 4 bit Binary Counter with Parallel Load

Post by Magneto » Sat Nov 14, 2009 10:20 pm

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//Binary counter with parallel load

module counter (Count,Load,IN,CLK,Clr,A,CO);
input Count,Load,CLK,Clr;
input [3:0] IN; //Data input
output CO; //Output carry
output [3:0] A; //Data output
reg [3:0] A;
assign CO = Count & ~Load & (A == 4'b1111);
always @ (posedge CLK or negedge Clr)
if (~Clr) A = 4'b0000;
else if (Load) A = IN;
else if (Count) A = A + 1'b1;
else A = A; // no change, default condition
endmodule
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