//Behavioral description of
//Universal shift register
module shftreg (s1,s0,Pin,lfin,rtin,A,CLK,Clr);
input s1,s0; //Select inputs
input lfin, rtin; //Serial inputs
input CLK,Clr; //Clock and Clear
input [3:0] Pin; //Parallel input
output [3:0] A; //Register output
reg [3:0] A;
always @ (posedge CLK or negedge Clr)
if (~Clr) A = 4'b0000;
else
case ({s1,s0})
2'b00: A = A; //No change
2'b01: A = {rtin,A[3:1]}; //Shift right
2'b10: A = {A[2:0],lfin}; //Shift left
//Parallel load input
2'b11: A = Pin;
endcase
endmodule
//One stage of shift register
module stage(i0,i1,i2,i3,Q,select,CLK,Clr);
input i0,i1,i2,i3,CLK,Clr;
input [1:0] select;
output Q;
reg Q;
reg D;
//4x1 multiplexer
always @ (i0 or i1 or i2 or i3 or select)
case (select)
2'b00: D = i0;
2'b01: D = i1;
2'b10: D = i2;
2'b11: D = i3;
endcase
//Structural description of
//Universal shift register
module SHFTREG (I,select,lfin,rtin,A,CLK,Clr);
input [3:0] I; //Parallel input
input [1:0] select; //Mode select
input lfin,rtin,CLK,Clr; //Serial inputs,clock,clear
output [3:0] A; //Parallel output
//Instantiate the four stages
stage ST0 (A[0],A[1],lfin,I[0],A[0],select,CLK,Clr);
stage ST1 (A[1],A[2],A[0],I[1],A[1],select,CLK,Clr);
stage ST2 (A[2],A[3],A[1],I[2],A[2],select,CLK,Clr);
stage ST3 (A[3],rtin,A[2],I[3],A[3],select,CLK,Clr);
endmodule
//D flip-flop
always @ (posedge CLK or negedge Clr)
if (~Clr) Q = 1'b0;
else Q = D;
endmodule
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Modelling a Shift Register with Verilog
Field-Programmable Gate Arrays
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