Mealy model in Verilog for Sequential Circuits

Field-Programmable Gate Arrays
Post Reply
User avatar
Magneto
Major
Major
Posts: 430
Joined: Wed Jul 15, 2009 1:52 pm
Location: London

Mealy model in Verilog for Sequential Circuits

Post by Magneto » Sat Nov 14, 2009 9:54 pm

m1.JPG
m1.JPG (21.46 KiB) Viewed 5171 times
m2.JPG
m2.JPG (11.53 KiB) Viewed 5171 times
//Mealy state diagram for the circuit in previous slide.
module Mealy_mdl (x,y,CLK,RST);
input x,CLK,RST;
output y;
reg y;
reg [1:0] Prstate, Nxtstate;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @ (posedge CLK or negedge RST)
if (~RST) Prstate = S0; //Initialize to state S0
else Prstate = Nxtstate; //Clock operations

always @ (Prstate or x) //Determine next state
case (Prstate)
S0: if (x) Nxtstate = S1;
S1: if (x) Nxtstate = S3;
else Nxtstate = S0;
S2: if (~x)Nxtstate = S0;
S3: if (x) Nxtstate = S2;
else Nxtstate = S0;
endcase
always @ (Prstate or x) //Evaluate output
case (Prstate)
S0: y = 0;
S1: if (x) y = 1'b0; else y = 1'b1;
S2: if (x) y = 1'b0; else y = 1'b1;
S3: if (x) y = 1'b0; else y = 1'b1;
endcase
endmodule
Post Reply

Return to “FPGA”