Modelling J-K Fiip Flop with Verilog

Field-Programmable Gate Arrays
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Magneto
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Modelling J-K Fiip Flop with Verilog

Post by Magneto » Sat Nov 14, 2009 9:33 pm

//JK flip-flop from D flip-flop and gates
module JKFF (Q,J,K,CLK,RST);
output Q;
input J,K,CLK,RST;
wire JK;
assign JK = (J & ~Q) | (~K & Q);
//Instantiate D flipflop
DFF JK1 (Q,JK,CLK,RST);
endmodule


// Functional description of JK flip-flop
module JK_FF (J,K,CLK,Q,Qnot);
output Q,Qnot;
input J,K,CLK;
reg Q;
assign Qnot = ~ Q ;
always @ (posedge CLK)
case ({J,K})
2'b00: Q = Q;
2'b01: Q = 1'b0;
2'b10: Q = 1'b1;
2'b11: Q = ~ Q;
endcase
endmodule
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