Modelling T Type Filp Flop in Verilog

Field-Programmable Gate Arrays
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Magneto
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Modelling T Type Filp Flop in Verilog

Post by Magneto » Sat Nov 14, 2009 9:30 pm

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//T flip-flop from D flip-flop and gates
module TFF (Q,T,CLK,RST);
output Q;
input T,CLK,RST;
wire DT;
assign DT = Q ^ T ;
//Instantiate the D flip-flop
DFF TF1 (Q,DT,CLK,RST);
endmodule

//T flip-flop
module T_FF (Q,T,CLK,RST);
output Q;
input T,CLK,RST;
reg Q;
always @ (posedge CLK or negedge RST)
if (~RST) Q = 1'b0;
else Q = Q ^ T;

//Stimulus for testing sequential circuit
module testTcircuit;
reg x,CLK,RST; //inputs for circuit
wire y,A,B; //output from circuit
// instantiate circuit
Tcircuit TC (x,y,A,B,CLK,RST);

initial
begin
RST = 0;
CLK = 0;
#5 RST = 1;
repeat (16)
#5 CLK = ~CLK;
end
initial
begin
x = 0;
#15 x = 1;
repeat (8)
#10 x = ~ x;
end
endmodule
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