Modelling D type Flip Flop in Verilog
Modelling D type Flip Flop in Verilog
output Q;
input D,control;
reg Q;
always @ (control or D)
if (control) Q = D; //Same as: if (control = 1)
endmodule
//D flip-flop
module D_FF (Q,D,CLK);
output Q;
input D,CLK;
reg Q;
always @ (posedge CLK)
Q = D;
endmodule
//D flip-flop with asynchronous reset.
module DFF (Q,D,CLK,RST);
output Q;
input D,CLK,RST;
reg Q;
always @(posedge CLK or negedge RST)
if (~RST) Q = 1'b0; // Same as: if (RST = 0)
else Q = D;
endmodule