Behavioral Modeling of Free Running Clock in Verilog

Field-Programmable Gate Arrays
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Magneto
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Behavioral Modeling of Free Running Clock in Verilog

Post by Magneto » Sat Nov 14, 2009 9:09 pm

//An example of a free-running clock
initial
begin
clock = 1’b0;
repeat (30)
#10 clock = ~clock;
end
initial
begin
clock = 1’b0;
#300 $finish;
end
always
#10 clock = ~clock
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