Behavioral modelling of 2-1 line Multiplexer in Verilog

Field-Programmable Gate Arrays
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Magneto
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Behavioral modelling of 2-1 line Multiplexer in Verilog

Post by Magneto » Sat Nov 14, 2009 9:02 pm

//Behavioral description of 2-to-1-line multiplexer
module mux2x1_bh(A,B,select,OUT);
input A,B,select;
output OUT;
reg OUT;
always @ (select or A or B)
if (select == 1) OUT = A;
else OUT = B;
endmodule
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