Writing a Test Bench for a multiplexer using Verilog

[Magneto]

//Stimulus for mux2x1_df.
module testmux;
reg TA,TB,TS; //inputs for mux
wire Y; //output from mux
mux2x1_df mx (TA,TB,TS,Y); // instantiate mux
initial
begin
TS = 1; TA = 0; TB = 1;
#10 TA = 1; TB = 0;
#10 TS = 0;
#10 TA = 0; TB = 1;
end
initial
$monitor("select = %b A = %b B = %b OUT = %b time = %0d",
TS, TA, TB, Y, $time);
endmodule

//Dataflow description of 2-to-1-line multiplexer
module mux2x1_df (A,B,select,OUT);
input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule